1. Field of the Invention
The invention relates to a method for controlling the reading-in of a clock signal to an input latch with the aid of a clock signal, and to an input circuit for an electronic circuit.
2. Description of the Related Art
Data signals are first read into an input latch in an integrated circuit before the data item which is represented by the data signal is made available to an internal circuit. The data signal is transferred to the input latch with the aid of a clock signal which is synchronized to the data signal.
Particularly in the case of a dynamic random access memory (DRAM) circuit, data signals are transferred by means of trigger signals, such as the DQS signal, which indicate the time at which the applied data should be read into the input latch. The applied data is generally transferred with an edge of the DQS signal or the clock signal.
Typically, the time at which the data signal is read-in is determined by a fixed time delay between the signal edge of the data signal which occurs at the change of the data item and the clock edge of the clock signal (e.g., the DQS signal) by means of which the data item is transferred to the input latch. This time delay is permanently set by means of delay elements which cannot be adjusted and leads to even minor process changes shifting this time delay, so that the reading-in time no longer corresponds to the selected optimum value.
Furthermore, the applied data item should be read in as quickly as possible so that the longest possible time period is available for further processing of the data item stored in the input latch. Since two or more data items which are applied to inputs of the electronic circuit should be read in with the clock signal, it is possible for the time period between the data signal edge and the clock edge to be insufficiently long for a data item to be reliably transferred to the input latch. The clock signal is thus set with respect to the signal edges of the data signals such that each of the data signals can be read in reliably. A sufficiently long time delay, which is defined in advance, is normally set between the signal edge of the data signal and of the clock signal for this reason in order to transfer each of the applied data signals reliably to the input latches with the greatest possible confidence. Consequently, subsequent circuits may have less time available to further process the input signal even though the data signals could have been transferred after a shorter delay time on a case-by-case basis.
Therefore, there is a need for a method as well as an input circuit to transfer data items which are applied to an input of an electronic circuit to an input latch as quickly as possible.